Stacked die package

ABSTRACT

A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board wiring. A reconstituted die, which includes a die surrounded by a frame, is mounted over the substrate. A top die is mounted over the reconstituted die. Both the reconstituted die and the top die are electrically connected to the substrate, e.g., by wire bonds.

This application is a divisional of patent application Ser. No.11/098,780, now U.S. Pat. No. 7,326,592, entitled “Stacked Die Package”filed on Apr. 4, 2005 and issued on Feb. 5, 2008, which application isincorporated herein by reference.

TECHNICAL FIELD

The invention relates to a stacked die package with integrated circuitssuch as memory devices or controllers.

BACKGROUND

The development of the application of integrated circuits shows thatmore complex functions are to be realized but there are limitations ofthe number of functions realizable on a single chip. Therefore,technologies for stacking of two or more dies with several functions andmethods for the mechanical and electrical interconnection with oneanother or with a base substrate which is the basis for stacking and formounting on a PCB (Printed Circuit Board) have been developed.

Several technologies for contacting different chips are known.Conventional technologies are using chip and wire bonding for contactingthe dies electrically. These are known processes with well-knownparameters. Using these technologies for stacked dies (FBGA: fine ballgrid array) the chips are placed one over another and the contacts ofthe dies are connected with corresponding contact pads on the substrateby wire loops performed by bonding.

For this wire bonding it is necessary to reroute the bond pads, whichare typically arranged in a row at the die center, to the edge of thedie, to avoid long wire bond loops (electrical performance). Thererouting (redistribution layer, RDL) is typically a metal line made ofcopper (basis metal), nickel (covering layer) and gold (suitable forcontacts). It can be built by electro- or electroless plating.

According to FIG. 1 (prior art), a first die 1 is bonded to thesubstrate or interposer board 2 by chip bonding. This can be performedby positioning an adhesive 3 between the first die 1 and the substrate2. Such adhesive 3 can be a tape with an adhesive coating on both sides.Then the bond pads 4 of the first die 1 are connected with contact pads5 on the substrate with wire loops 6 by wire bonding.

Now a distance element or spacer 7 must be mounted on the top side ofthe first die 1. This is possible with known technologies like diebonding with adhesive 8 or a tape. The spacer 7 is necessary forprotecting the wire loop 6 between the bond pad 4 on the first die 1 andthe contact pad 5 on the substrate 2. The spacer 7 can be a silicon die,an adhesive tape with a sufficient thickness or any other suitablematerial, but the dimensions of the spacer 7 must be smaller than thedimensions of the die 1.

After this step, a next die 9 can be mounted on the spacer 7 withadhesive 10 or tape and then the same connecting procedure must beperformed like for the first die 1 including connecting the bond pads 11on the second die 9 with contact pads 5 on the substrate 2 by wire loops12. The stacked structure is now protected (backside- and edge protect)by a mold encapsulant 13. The substrate 2, opposite the stacked dies 1,9 is provided with solder balls 14 which are electrically connected(normally soldered) to the contact pads 5 on the substrate 2.

It seems to be clear that this is a very expensive technology (serialprocesses with high accuracy), even in case that more than two dies arestacked.

The high number of interfaces (due to the spacer) results in a lowerprocessing yield. Additionally, the top die has to be bonded onoverhang, which is a critical process for very thin dies. These areneeded because the absolute height of the package is increased by thespacer, but the height restrictions of stacked packages neverthelesshave to be fulfilled. Furthermore, the reliability (e.g., moistureresistance) is a critical aspect due to the high number of interfaces ifa spacer is used in a wire-bonded stacked package.

An example for a package of semiconductor chips is known from U.S.Patent Application Publication 2003/0015803 A1. The semiconductor chipshave identical dimensions and are spaced apart by spacers of smallerlateral dimensions, preventing the chip from directly contacting to theneighbor and allowing wire-bonding of each of the stacked chips to thebonding pads on a carrier.

Another stacked multi-chip module and a method for manufacturing astacked multi-chip module is described in EP 0 575051 B1. According tothis document, a first element (die) is mounted on a substrate by usingan adhesive material. A second element (die) is mounted to the firstagain by using an adhesive material. The third die should be at leastpartially supported by the second die and the second die should be atleast partially supported by the first die. Furthermore, the second dieis positioned such that the electrical contacts are exposed andaccessible for making fine wire connections thereto. Likewise, the thirddie may be positioned such that electrical contacts of the second dieare exposed and accessible for making fine wire connections thereto.Although the upper dies are progressively smaller in size.

The problem of this prior art is that the dies must be equal in size butit is possible to stack very thin dies.

SUMMARY OF THE INVENTION

In one aspect, the present invention overcomes the limitations of theprior art and simplifies the assembly technology.

In another aspect, the invention increases the reliability of a stackeddie package by decreasing the number of interfaces within the package.

In a further aspect, the invention decreases the total height of thepackage or increases the number of chips in the package with maintainingthe total package height.

According to an embodiment of the invention, the bottom die can bemodified in advance to die bonding to provide additional area around thesilicon edge. That way the use of a spacer is not needed. The bottom dieis embedded in a polymer material by molding (reconstitution) resultingin a frame around the die. This frame is a fan-out area, the chip areais now larger than the bare silicon of the die. The redistribution linethat is used to distribute connections from the pads on the chip to theedges of the die package can be elongated to the edge of the frame. Theposition for the bond wire interconnect is transferred to the edge ofthe frame as well. That way the bottom die on the substrate is providedwith a larger area than a next die, which can be die bonded with anadhesive at the top side of the first reconstituted die. The area out ofthe die shadow of the upper die can now used to connect the first diewith the substrate or the bottom die by wire bonding.

The result is that a spacer is no longer necessary, all process steps,necessary for assembling the spacer can be left out. This leads to lowerpackaging costs and less reliability issues due to a reduced number ofmaterial interfaces.

Another feature of the invention is that more dies can be stacked at agiven total height, or the total package height of two stacked dies canbe reduced.

One feature of the preferred embodiment of the invention is areconstituted die, surrounded by a polymer. A surrounding rim isperformed, protecting the backside and the edge of the silicon die, andnot covering the active side of the die. It is possible to provide bondpads outside the silicon area (fan-out) on the RDL.

The reconstituted chip is produced in the well-known wafer-leveltechnology. Front-end tested good dies after dicing are picked up andplaced face down on an adhesive tape with any distance from each other(fan-out area). Then, the dies on the tape are reconstituted to areconstituted wafer-by-wafer molding with the mentioned polymer.

An RDL is formed (e.g., sputter and plate) from the center row bond padsto the edge of the reconstituted die on the wafer. At the edge of thepolymer embedded die, this RDL is used as new bond pad for the wire bondto the substrate.

After applying the RDL, the reconstituted wafer is diced into individualreconstituted dies, each provided with a polymer frame. With thisrerouting of the bond pads, it is possible to stack dies with a minorbasic (fan-out) area (as the bottom reconstituted die) or standardfront-end dies on the reconstituted bottom die. Therefore, only anadhesive without any spacer is needed.

It is also possible to stack dies with originally equal dimensions dueto the provided frame, which is increasing the dimension of the bottomdie.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawing, in which:

FIG. 1 illustrates stacked dies on an interposer board according to theprior art;

FIG. 2 illustrates an embodiment of stacked dies according to apreferred embodiment of the invention with a reconstituted die on aninterposer board and a second die mounted on the reconstituted die;

FIGS. 3 a to 3 h show the manufacturing steps to realize reconstituteddies;

FIGS. 4 a to 4 f illustrate the process flow for stacking dies accordingto a preferred embodiment of the invention; and

FIG. 5 illustrates an example with three dies stacked on a substrate andeach of the stacked dies electrically connected with the interposerboard.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 2 illustrates an embodiment of the invention with an interposerboard 20 with a reconstituted die 21 mounted on the interposer board 20.The reconstituted die 21 is mounted on the interposer board 20 by aliquid adhesive 22 or an adhesive tape 22. The reconstituted die 21 isprovided with a frame 23 to increase the die area (fan-out) to thementioned reconstituted die 21. The top or active surface of thereconstituted die 21 is provided with RDL layer 24, which reroute thebond pads 25 arranged in a center row on the reconstituted die 21 towire bond pads 26 positioned on the frame 23. The wire bond pads 26 canbe connected with landing pads 27 on the interposer board 20 by wireloops 28. This interconnection can also take place in a later step afterassembly of the top die(s).

Then a second die 29 is die bonded on the top surface of thereconstituted die 21 with an adhesive glue or tape 30. This die 29 canalso be a reconstituted die with a smaller fan-out area than the bottomdie for stacking three or more dies, or it is a front-end-chip withoutfan-out area, but with an RDL. The second die 29, and all followingdies, is also provided with an RDL to reroute the bond pads 31 arrangedin a centre row to wire bond pads 32 on the rim of the second die 29.These wire bond pads 32 are connected with landing pads 33 on theinterposer board 20 or to the bond pads of the chip below by wire loops34. The arrangement with the two stacked dies is surrounded by anencapsulant 35 so that the wire loops 28, 34 are protected.

The interposer board 20 is provided with solder balls 36 at the bottomside, which are connected with the landing pads 27, 33.

FIGS. 3 a to 3 h show the simplified manufacturing steps to realizereconstituted dies 21. To start, a carrier plate 40, which can be asilicon wafer or another suitable plate is provided. This plate 40 isnecessary only temporarily. The plate 40 is illustrated in FIG. 3 a. Areleasable adhesive tape 41 is mounted on the carrier plate, as shown inFIG. 3 b.

Referring to FIG. 3 c, front-end tested good dies 42 are placed on theadhesive 41 with sufficient gaps between each other (fan-out area) withthe active side in direction to the carrier plate. The backside and theedges of the placed dies are now molded to a reconstituted wafer, a moldencapsulant, 43 by wafer molding, as shown in FIG. 3 d. In this manner,each die 42 is surrounded by a frame 44.

After this molding step the carrier plate 40 can be removed as shown inFIG. 3 e. FIG. 3 f illustrates the simplified step of applying the RDL45 on the active surface of the die 42 over the interface between thechip and surrounding polymer frame 44 by sputtering, lithography andplating. The RDL can also be electroless plated or printed with anyconductive material. Then a backside grinding of the die 42 is possibleto remove mold compound from the backside of the dies and to decreasethe thickness of the dies 42. This is shown in FIG. 3 g. Referring toFIG. 3 h, the reconstituted dies 21 are now separated by dicing in a waythat each die 42 is surrounded by an individual frame 49.

FIGS. 4 a to 4 f illustrate the simplified process flow for stacking oftwo dies according an embodiment of the invention by way of crosssections. Referring first to FIG. 4 a, an interposer board 20 isprovided with a die adhesive or adhesive tape 22 on its top surface atthe area at which a reconstituted die 21 should be die bonded. Theadhesive can be printed or the tape can be laminated in a separate stepbefore die bonding. The interposer board is provided with landing pads27, 33 and solder pads 46 for applying solder balls 36 (shown in FIG. 4f). The reconstituted die 21 (e.g., according FIG. 3) is die bonded tothe interposer board 20.

Another adhesive layer or adhesive tape 30 is applied on the bottom dieby printing, dispensing or any other technique. The next die 29 with asmaller outer dimension than the reconstituted die below 21 is diebonded now on the die below. This die 29 can be another reconstituteddie or a standard front-end silicon die without fan-out area. Now thebond pads 26, 32 are connected with the landing pads 27, 33 by wireloops 28, 34, respectively. The dies can be connected as shown in FIG. 4d or the top die 29 can be connected with the die below, and this diecan afterwards be connected with the interposer board 20. This bondingtechnique is well known and saves space in lateral dimensions. Only thechip select connection must be bonded separately between the dies.

FIG. 4 e shows the stacked die assembly according to FIG. 3 aftermolding with a mold encapsulant 43 for mechanical protection of thesilicon dies 21, 29 and wire loops 28, 34. Solder balls 36 are assembledas seen in FIG. 3 f.

FIG. 5 shows an example with three dies 21, 29, 47 stacked on asubstrate 20. The dies 21, 47 are reconstituted dies according FIG. 3 hand the reconstituted die 47 has smaller dimensions than thereconstituted die 21. The frame 49 (fan-out area) of the reconstituteddie 47 is smaller than the frame 23 of the reconstituted die 21. The topdie 29 can be a bare die without any frame but provided with an RDL 45or a reconstituted die as well. The lateral dimensions of the dies mustshrink from bottom to top, so that wire bonding is possible from eachlevel to the landing pads 27, 33 on the interposer board. The electricalconnections are performed similar to FIG. 4 d.

It is noted that the number of stacked dies is not limited.

In each of the above-described embodiments, an RDL 45 was provided toredistribute center bond pads to the peripheral of the chip. It isunderstood, however, that concepts of the present invention apply tochips that include bond pads formed at the peripheral. For these chips,the RDL 45 may not be necessary or may be necessary only to redistributeperipheral pads on the die to the frame 23. As a result, the inventionapplies equally to embodiments that do not include an RDL.

1. A stacked die package, comprising: a substrate; a contact area on atop surface of the substrate and landing pads surrounding the contactarea; solder pads on an opposite side of the substrate, the solder padsbeing electrically connected with the landing pads by inner boardwiring; a reconstituted die mounted over the substrate, thereconstituted die comprising a die surrounded by a frame, wherein thereconstituted die comprises a redistribution layer (RDL), routing fromcenter row bond pads on the die to wire bond pads on the frame; a topdie mounted over the reconstituted die.
 2. The stacked die packageaccording to claim 1, further including a first adhesive between thereconstituted die and the substrate and a second adhesive between thereconstituted die and the top die.
 3. The stacked die package accordingto claim 1, further comprising wire loops between bond pads on thereconstituted die and the landing pads on the substrate and also betweenbond pads on the top die and the landing pads on the substrate.
 4. Thestacked die package according to claim 1, wherein the frame comprises apolymer or metal material.
 5. The stacked die package according to claim1, further comprising first wire loops between the wire bond pads on theframe of the reconstituted die and the landing pads on the substrate andsecond wire loops between bond pads on the top die and the landing padson the substrate.
 6. The stacked die package according to claim 5,wherein the reconstituted die, the top die and the first and second wireloops are embedded in a mold compound.
 7. The stacked die packageaccording to claim 1, wherein the substrate comprises an interposerboard.
 8. The stacked die package according to claim 1, furthercomprising a second reconstituted die that includes a second diesurrounded by a second frame, the second reconstituted die being smallerthan the reconstituted die but larger than the top die, the secondreconstituted die mounted over the reconstituted die, the top die beingmounted over the second reconstituted die.
 9. A stacked die package,comprising a substrate; a contact area on a top surface of thesubstrate; landing pads on the top surface of the substrate surroundingthe contact area; solder pads on a bottom surface of the substrate, thesolder pads being electrically connected with the landing pads by innerboard wiring; a first reconstituted die mounted on the contact area ofthe substrate board, the first reconstituted die surrounded by a firstframe, wherein the first reconstituted die comprises a firstredistribution layer over a first active surface; and a top die over thefirst reconstituted die.
 10. The stacked die package of claim 9, whereinthe top die is electrically connected to the substrate.
 11. The stackeddie package of claim 9, wherein the first reconstituted die iselectrically connected to the substrate, wherein the electricalconnection comprises wirebonding from first bonding pads disposed on thefirst reconstituted die to landing pads on the substrate.
 12. The methodof claim 11, wherein the first bonding pads are disposed over the firstframe of the first reconstituted die, the first frame comprising anencapsulant.
 13. The stacked die package of claim 9, further comprisinga second reconstituted die mounted between the first reconstituted dieand the top die, the second reconstituted die surrounded by a secondframe, wherein dimensions of the second frame are smaller thandimensions of the first frame.
 14. The stacked die package of claim 13,wherein the second reconstituted die comprises a second redistributionlayer over a second active surface.
 15. The stacked die package of claim13, wherein the second reconstituted die is electrically connected tothe substrate, wherein the electrical connection comprises wirebondingfrom second bonding pads disposed on the second reconstituted die tolanding pads on the substrate.
 16. The stacked die package of claim 15,wherein the second bonding pads are disposed over the second frame ofthe second reconstituted die, the second frame comprising theencapsulant.
 17. The stacked die package of claim 13, further comprisinga first adhesive between the first reconstituted die and the substrateand a second adhesive between the second reconstituted die and the topdie.
 18. A stacked die package, comprising: a substrate; a contact areaon a top surface of the substrate; landing pads on the top surface ofthe substrate surrounding the contact area; solder pads on a bottomsurface of the substrate, the solder pads being electrically connectedwith the landing pads by inner board wiring; a first reconstituted diemounted on the contact area of the substrate board, the firstreconstituted die surrounded by a first frame, wherein the firstreconstituted die comprises a first redistribution layer over a firstactive surface, and wherein the first reconstituted die comprises aredistribution layer (RDL), routing from center row bond pads on thefirst reconstituted die to first wire bond pads on the first frame; asecond reconstituted die mounted over the first reconstituted die, thesecond reconstituted die surrounded by a second frame, whereindimensions of the second reconstituted die are smaller than dimensionsof the first reconstituted die; and a top die over the secondreconstituted die, wherein dimensions of the top die are smaller thandimensions of the second reconstituted die.
 19. The stacked die packageof claim 18, wherein the second reconstituted die comprises aredistribution layer (RDL), routing from center row bond pads on thesecond reconstituted die to second wire bond pads on the second frame.20. The stacked die package of claim 19, wherein the top die comprises aredistribution layer (RDL), routing from center row bond pads on the topdie to wire bond pads on a rim of the top die.